1. Field of the Invention
The present invention relates to a semiconductor memory device and, for example, to a data input/output circuit included in a semiconductor memory device.
2. Description of the Related Art
The data input/output speed of semiconductor memory devices is steadily increasing recently along with the progress of microfabrication of elements. Tests coping with the high-speed data input/output operation must be executed for such semiconductor memory devices.
However, a tester capable of conducting tests coping with the high-speed data input/output operation is expensive. For this reason, the cost of the test of semiconductor memory devices increases. More specifically, to execute a data input/output test for a semiconductor memory device capable of an input/output operation in synchronism with a high-frequency clock, a tester is necessary, which can transmit data at a speed corresponding to the high-frequency clock in a data write. In a data read, the tester must be able to compare output data with an expected value in a short time corresponding to the high-frequency and determine whether correct data is output. However, a tester capable of such a high-speed operation is expensive, and the cost of the test of semiconductor memory devices increases.
A semiconductor memory device has been proposed as a prior art related to the present invention. This device allows pulse generation of an internal sync signal ICLK in accordance with not only transition of an external clock CLK from Low level to High level but also level transition of another input. Hence, even a memory tester that obtains only a low-frequency external clock can conduct a test at a higher frequency beyond the performance of the memory tester (Jpn. Pat. Appln. KOKAI Publication No. 11-66894).